An example of a VLIW processor is the TM-1000 processor (TriMedia) of Philips Electronics. This processor is described in, for example, European patent application No. EP 605 927 (equivalent to U.S. Ser. No. 07/999,080 now abandoned; PHA 21777). In a VLIW processor, parallel execution of instructions is obtained by combining multiple basic machine commands in a single long instruction word. Typically, each such basic command represents a RISC operation. Per clock cycle, a long instruction word is supplied to a parallel arrangement of functional units that operate in lock-step. A respective one of the commands is supplied to a relevant one of the units. Typically, a unit performs pipelined execution.
The TM-1000 processor issues the commands in parallel, each in a respective issue slot of the very long instruction word issue register. Each issue slot is associated with a respective group of functional units and with two read ports and one write port to the register file. A particular command is directed to a specific one among the functional units of the group that is associated with the particular issue slot. The command typically comprises an opcode, two source operand definitions and a result operand definition. The source operand definitions and the result operand definition refer to registers in the register file. During execution of the command, the source operands are read from the particular issue slot by supplying fetch signals to the read ports associated with the issue slot in order to fetch the operands. Typically, the functional unit receives the operands from these read ports, executes the command according to the opcode and writes back a result into the register file via the write port associated with the particular issue slot. Alternatively, commands may use fewer than two operands and/or produce no result for the register file.
A typical program for the VLIW processor is translated into a set of commands for the functional units. A compile time scheduler distributes these commands over the long instruction words. The scheduler attempts to minimize the time needed to execute the program by optimizing parallelism. The scheduler combines commands into instruction words under the constraint that the commands assigned to the same instruction can be executed in parallel and under data dependency constraints.